This invention relates generally to a method and circuit for establishing an operating point of a field effect transistor (FET) and more particularly to the design of FET integrated circuits. This invention is applicable to GaAsFET, and silicon MOSFET, JFET and MESFET integrated circuits.
All active circuits require an operating point be established to determine the operational characteristics of the active devices. In analog FET circuits, it is usually desirable to set the operating point of the transistor, i.e., the drain-to-source voltage V.sub.DS, at a point above the knee, i.e., the saturation or high-gain region, as opposed to below the knee, i.e., the triode, ohmic or low-gain region.
This can be done by picking a drain-source voltage V.sub.DS much larger than needed. For many applications, this design strategy is satisfactory and it is widely used by designers. It can be undesirable to do so, however, in situations in which a limited power supply voltage is available or in which the circuit has many transistors in series. It becomes necessary to more accurately divide the available voltage among the transistors to assure that all of the transistors operate in saturation.
From the prior art literature and conventional practice, it appears that no one in the field of analog FET integrated circuit design has seriously considered picking the minimum drain-source voltage required, knowing how the transistors operate, so as to insure that the operating point is above the knee without having unnecessary excess voltage, and implemented such a circuit. Conventionally, designers make a crude approximation with voltage dividers, stacked diodes and the like, but typically get a larger drain-source voltage than is required.
Also, many prior biasing circuits have adverse temperature-dependent operating characteristics. Once an operating point is selected, it is desirable to have any temperature-dependent changes to be in a direction that would tend to keep the operating point above the knee. Many circuits change in the wrong direction. For example, it is desirable for the bias circuit that establishes the drain-source voltage V.sub.DS for an FET to increase V.sub.DS in a known way. This is because the pinchoff voltage of the transistor becomes more negative (its magnitude increases) as temperature increases. Unfortunately, if one uses a stack of diodes to set V.sub.DS, the drain-source voltage becomes less negative with temperature. To deal with this problem, designers conventionally use a larger V.sub.DS with sufficient margin to maintain the operating point above the knee while accommodating temperature variations. This approach works in many situations, but has some problems and restricts the freedom to create some circuits that a designer might otherwise use.
Accordingly, a need remains for a better way to set the operating point of a field effect transistor, that provides sufficient but not excessive voltage reliably to operate the FET in saturation.